`timescale 1ns / 1ps

module  tb_sm3;
reg clk,rst_n;
reg [31:0] msg_inpt_d;
reg [3:0] msg_inpt_vld_byte;
reg msg_inpt_vld,msg_inpt_lst;
wire msg_inpt_rdy;
wire [255:0] cmprss_otpt_res;
wire cmprss_otpt_vld;

sm3_top sm3(
            .clk(clk),
            .rst_n(rst_n),
            .msg_inpt_d(msg_inpt_d),
            .msg_inpt_vld_byte(msg_inpt_vld_byte),
            .msg_inpt_vld(msg_inpt_vld),
            .msg_inpt_lst(msg_inpt_lst),
            .msg_inpt_rdy(msg_inpt_rdy),
            .cmprss_otpt_res(cmprss_otpt_res),
            .cmprss_otpt_vld(cmprss_otpt_vld)
            );

always #10 clk = ~clk; 

initial
    begin
        clk = 0;
        rst_n = 0;
        msg_inpt_d = 32'h0;
        msg_inpt_vld_byte = 4'h0;
        msg_inpt_vld = 0;
        msg_inpt_lst = 0;
        #20
        rst_n = 1;
        msg_inpt_d = 32'hf93719cd;
        msg_inpt_vld_byte = 4'hf;
        msg_inpt_vld = 1;
        msg_inpt_lst = 1;
    end 
    
endmodule
        